DBLBUF_ENA=DISABLED, CNT_ENA=DISABLED, INT_DMA_REQ=CLR, DMA_ENA=DISABLED
DAC control register.
| INT_DMA_REQ | DMA request 0 (CLR): This bit is cleared on any write to the DACR register. 1 (SET): This bit is set by hardware when the timer times out. |
| DBLBUF_ENA | DMA double-buffering 0 (DISABLED): DACR double-buffering is disabled. 1 (ENABLED): When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter. |
| CNT_ENA | DMA time-out 0 (DISABLED): Time-out counter operation is disabled. 1 (ENABLED): Time-out counter operation is enabled. |
| DMA_ENA | DMA enable 0 (DISABLED): DMA access is disabled. 1 (ENABLED): DMA Burst Request Input 15 is enabled for the DAC (see Table 136). |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |